The present application relates to a semiconductor integrated circuit device (or semiconductor device), and can be applied, for example, to a device in which a semiconductor chip is mounted over a wiring board.
Japanese Unexamined Patent Application Publication No. 2008-300469 (Patent Document 1) relates to a laminated chip using a TSV (Through-Silicon Via) technique. In Patent Document 1, a chip laminated structure is disclosed, in which the uppermost layer chip is connected to lower chips including a power supply via a TSV, and further connected to the outside via a bonding wire.
Japanese Unexamined Patent Application Publication No. 1996-274127 (Patent Document 2) or U.S. Pat. No. 5,670,802 (Patent Document 3) corresponding to Patent Document 2 relates to an LSI (Large Scale Integration) having many terminals. In Patent Document 2 and Patent Document 3, a technique is disclosed, in which a power supply terminal, etc., in an interface circuit and that in an internal circuit are taken out independently by using bonding wires.
Japanese Unexamined Patent Application Publication No. 2008-4714 (Patent Document 4) relates to a laminated chip using a TSV technique. In Patent Document 4, a technique is disclosed, in which power and a reference potential are supplied to upper chips via bonding pads and bonding wires, and signals are communicated from upper chips to lower chips via through electrodes and capacitive coupling.
Japanese Unexamined Patent Application Publication No. 2011-216592 (Patent Document 5) or U.S. Unexamined Patent Application Publication No. 2011-242714 (Patent Document 6) corresponding to Patent Document 5 relates to ESD (Electrostatic discharge) regarding the interface of a semiconductor chip. In Patent Document 5 and Patent Document 6, a technique is disclosed, in which ground terminals are used in common in an internal circuit and an interface circuit in order to reduce the number of electrode pads.